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Any number of BOM Sets can be defined, click the icon to apply that BOM Set. The option is accessed from the UI Theme Current drop down menu in the System вЂ“ ViewВ page of the PreferencesВ dialog.ДЄ common requirement during BOM generation is the need to output the BOM in a number of different layouts вЂ“ each displaying different data for various post-design processes, such as purchasing, board assembly preparation, and so on.ДЄctiveBOM now supports BOM Sets, each BOM Set captures the current layout and configuration of the BOM Items grid, saving it as a named Set. Light/Dark Theme choiceДЄltium Designer now includes the option to switch between its default 'dark' GUI theme and a new Altium Light Gray theme. To correct this, flush the Acrobat Reader cache using the Purge Cache Contents button in the Search section of the readerвЂ™s Preferences dialog.

#UPDATE TO ALTIUM DESIGNER 18 PDF#

Note that Acrobat Reader will retain the results of previous searches, and may not deliver the expected search results when an existing PDF has been updated from Altium Designer.

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In Altium Designer, when configuring an OutJob to generate PDF documentation outputs containing True Type fonts, check the TT fonts printout option in the PCB Printout Properties dialog to enable full TTF support.

#UPDATE TO ALTIUM DESIGNER 18 GENERATOR#

The documentation PDF generator has been updated to support vector rather than rasterized True Type fonts, which ensures clean font rendering in the PDF output and allows text to be searched and selected in the external PDF reader. True generation of True Type Fonts in PDF Outputs The dialog option is also available when any of the 3D export formats have been added as an Export Output in an Output Job.

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This choice is now included as a Skip Free 3D Bodies option in the Export Options dialog, which is opened from the File В» Export В» command, where format is PARASOLID, STEP 3D or VRLM. When exporting a 3D model of a board design to the MCAD domain it may be desirable to exclude freely placed 3D body models, such as an enclosure that has been previously imported from MCAD.

The center point in a line between two snap points (Spacebar mode).

The 90В° locations (points crossing the orthogonal axes) around a hole circle.

The enhanced snapping location options also improve the ability to measure critical span distances in 3D objects. To improve the convenience and accuracy of positioning 3D models in a PCB design, support has been added for a range of new snapping point placement options for 3D models. Along with allowing back drilling from the board surface to any internal layer, the process and its Design Rule now recognizes layer connections made to copper objects such as polygons, fills and regions. Control over the handling of the Diff Pair Net classes can be specified in the Comparator and ECO tabs of the Options for PCB project dialog ( Project В» Project Options).Д¬ontrolled Depth Drilling, or Back Drilling, in Altium Designer has been improved to support the PCB Via stub removal technique for any defined Back Drill Pairs. When passed to the PCB via an Engineering Change Order (ECO), the class becomes available as a Diff Pair Class to apply to PCB Differential Pair Routing Rules. Updates Create Differential Pair classes in the Schematic EditorДЄ dedicated Differential Pair Class can now be defined at the schematic level by adding the new Diff.PairNetClass class type to Differential Pair Directives through the Properties panel. в–є See the FPGA Pin Mapper Quick Guide for an overview of using the Pin Mapping feature. The pin data exchange between the domains is therefore bidirectional, which enables an iterative and cooperative approach to FPGA pin layout through pin swapping, while avoiding the errors of manually passing pin data between domains.

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Altium Designer will detect any changes made to that file and offer a range of pin data synchronization choices, including the option to update the external file to match the net pin names in Altium Designer. Included in Altium Designer as the Pin Mapper dialog, it allows a link to be specified between a schematic component and an external *.csv pin information file that has been generated by the FPGA tool. It offers an interactive mechanism for exchanging pin/net definition data between the FPGA (or Microcontroller) and PCB domains via the common format of csv pin report/information files. The FPGA Pin Mapping feature has been developed to expedite the process of achieving the optimal topology for pin programmable devices in PCB layouts. The FPGA Pin Mapper is currently a beta version.

Update to altium designer 18